This invention relates generally to an arithmetic operator used for digital processing circuits and more particularly to a synchronous latched multivalued full adder.
Digital signal processing circuits are being implemented as large-scale-integrated (LSI) circuits on chips by using conventional photomasking and silicon surface processing technology. The size and complexity of some LSI circuits have grown to the extent that this conventional technology is a limitation on the ability to integrate them on the chips. That is, the number of transistors and resistors, together with the number of metal signal line interconnections, that can be integrated on a chip of given size is limited by this technology.
Typically, the LSI circuits on the chip embody binary logic processing binary signals. Since the binary signals may assume only two states, i.e., logic 0 or logic 1, the amount of information on the metal signal line interconnections carrying these signals is limited. If the circuits must process greater amounts of information, the number of metal signal line interconnections must increase.
As an alternative to binary logic, multivalued logic is being considered for use on LSI circuits. The term "multivalued" is used in the art to mean signals that may assume more than two states, i.e., three or more. For example, a quaternary or 4-valued logic circuit is a circuit that processes a signal that may assume any one of four states of logic 0, logic 1, logic 2, or logic 3. A signal that may assume four states thus contains twice the amount of information of a binary signal which can assume only two states. Consequently, multivalued logic circuits can be implemented with fewer metal signal line interconnections than binary logic circuits, since each metal signal line interconnection can carry signals having more information than binary logic circuits. As a corollary, the same number of metal signal line interconnections may be used on a chip of a given size as for binary logic, but with an increase in signal processing capability.
While conventional multivalued logic circuits have the advantage of reducing the number of metal signal line interconnections that is required for a given LSI circuit, the number of transistors and resistors that is required to implement the circuit is not necessarily reduced. Therefore, there is still a limitation on the size and complexity of LSI processing circuits that can be implemented on a chip of given size. This is not insignificant since a circuit may require many thousands and tens of thousands of integrated transistors and resistors.
For example, in performing an arithmetic function, such as an add function, a quaternary logic full adder adds two 4-valued inputs A and B, and a binary input C.sub.i, which is a carry input, to yield a 2-digit, base-four output word CS, where C is the carry and S is the sum. In performing this function, the full adder decodes the total value of the sum of inputs A, B and C.sub.i to produce the sum S and the carry C. Thereafter, the storage of the sum S and carry C outputs is usually done in two separate latches. As a result, a number of transistors and resistors is required by the full adder to perform its function, while an additional number of transistors and resistors is required for each latch to perform the storage function. A complex LSI circuit will usually have many such full adders and latches.